Electromechanical micromirror devices have drawn considerable interest because of their application as spatial light modulators (SLMs). A spatial light modulator requires an array of a relatively large number of such micromirror devices. In general, the number of devices required ranges from 60,000 to several million for each SLM. Despite significant advances that have been made in recent years, there is still a need for improvement in the performance and manufacturing yields of electromechanical micromirror devices.
An example of an early generation prior art device is disclosed in U.S. Pat. No. 4,592,628. U.S. Pat. No. 4,592,628 describes an array of light reflecting devices on a substrate. Each device comprises a hollow post and a deflectable polygonal mirror attached thereto. Each mirror acts as a deflectable cantilever beam. The mirrors are deflected by a beam of electrons from a cathode ray tube. The hollow posts act as scattering and diffraction sites. Since the mirror is the deflectable cantilever beam, the mirror will not be flat when deflected. As a result, the light throughput of the mirror into a certain acceptance cone is not as good as if the mirror were optically flat. Preferred mirror shapes include squares, rectangles, and hexagons.
Another early generation device is disclosed in U.S. Pat. No. 4,229,732. In this case, addressing circuits using MOSFETs were fabricated on the surface of the substrate. Deflectable metallic mirrors were also fabricated on the surface of the substrate. The metallic mirrors are not flat when deflected. As a result, the light throughput into a certain acceptance cone is not as good as if the mirror were optically flat. Since the MOSFET circuits and mirrors could not overlap, the fill factor of the array was not as high as if the mirrors could cover the entire surface area.
A 1st generation Texas Instruments, Inc. (TI) device is described in U.S. Pat. No. 4,662,746. A micromirror is suspended by 1 or 2 hinges. If suspended by 1 hinge, the micromirror deflects like a cantilever beam. If suspended by 2 hinges, the micromirror deflects like a torsion beam. Addressing electrodes are located below the micromirrors and addressing circuits are located at the same level in the substrate as the addressing electrodes. This means that the fill factor is improved. FIG. 1a of this patent shows a perspective view of a micromirror. The micromirror has plasma etch access holes that are used for plasma etching the underlying sacrificial layer. These plasma etch access holes lower the fill factor and increase scattering and diffraction. Note that the hinge metal layer has a substantially smaller thickness than the beam metal layer. This means that most of the bending occurs at the hinge and not at the beam. This design improves the flatness of the mirror; however, flatness would be improved further by placing the hinge at a lower level than the mirror, as discussed below.
A 2nd generation TI device is described in U.S. Pat. No. 5,583,688. A 2nd generation TI device is one in which the torsion hinge is at a different level than the reflective mirror. As described more fully in U.S. Pat. No. 5,583,688, the mirror is supported by a mirror support post, which is attached to the torsion hinge by a yoke. In U.S. Pat. No. 5,583,688, the mirrors are actuated by electrostatic forces between the mirror and address electrodes. The device is designed such that the mirror edge do not touch the address electrodes. Instead, the yoke edge touches the yoke landing site. In this design, the mirror is expected to remain flat during operation. The fill factor is relatively high because the CMOS circuits and torsion hinges are hidden under the mirror.
FIG. 2 of U.S. Pat. No. 5,583,688 shows that the mirror support post forms a rectangular recess in the mirror surface. This arises because the metallic mirror layer and mirror support post are formed by sputter deposition on a sacrificial layer that has had a via formed in it. It can be understood that the rectangular recesses are a source of scattering and diffraction.
The problem of the diffraction from the mirror support post (also called spacervia) is discussed in Dewald et al, “Advances in contrast enhancement for DLP projection displays,” Journal of the SID, vol. 11/1, pp. 177-181 (2003). The projection of the propagation vector of the incident light beam on the substrate plane is called the illumination axis. In an earlier design, the rectangular edges of the spacervia were placed parallel and perpendicular to the illumination axis. In the earlier design, the dimensions of the spacervia were approximately 4 microns by 3 microns. In an improved design, called small rotated via (SRV), the dimensions of the spacervia were reduced to 2 microns by 3 microns. The area of the spacervia was reduced by 50%. Furthermore, the spacervia was rotated by 45 degrees relative to earlier designs, such that no rectangular edge of the spacervia was perpendicular to the illumination axis. As a result of these improvements, contrast increased by 50%.
The problem of diffraction effects is discussed in U.S. Pat. No. 6,469,821. It is shown that modified mirror designs are preferable. An improved mirror has 2 sides that are straight and parallel to the illumination axis. Instead of 2 additional sides that are perpendicular to the illumination axis, a modified mirror provides a leading jagged edge and a trailing jagged edge, such that no side is perpendicular to the illumination axis. If the spacervia edges are also not perpendicular to the illumination axis, then no edge of the mirror is perpendicular, and as a result, diffraction is reduced. Furthermore, it is shown that the overall size and cost of the display can be reduced by placing the light source relative to the micromirror array such that the illumination axis is parallel to 2 sides of the rectangular array and perpendicular to the remaining 2 sides of the rectangular array. Despite these improvements, the limitation of U.S. Pat. No. 6,469,821 is that it does not disclose how to obtain an optically flat mirror, i.e. one that eliminates diffraction effects from the spacervia. Furthermore, the device architecture that is described in U.S. Pat. No. 6,469,821 is one in which the mirrors are fabricated on top of CMOS circuits. There are additional problems associated with this architecture as discussed below.
Micromirrors that are described in U.S. Pat. No. 4,662,746 and U.S. Pat. No. 5,583,688 are fabricated on top of CMOS circuits. There may be manufacturing problems associated with the fabrication of micromirrors on top of CMOS circuits. This issue is discussed in U.S. Pat. No. 5,216,537. In this patent, it is discussed that the surface of the CMOS chip has certain manufacturing artifacts, namely aluminum hillocks, pinholes, nonplanar surfaces, and steep sidewalls in the protective oxide at edges of aluminum leads. In response to these problems, U.S. Pat. No. 5,216,537 discloses an improved architecture in which an air gap is provided between the top surface of the CMOS chip and the mirror addressing electrodes. A further advantage of this approach is that because of the low dielectric constant of air, parasitic coupling between the CMOS and the micromirror is reduced.
The placement of CMOS circuits directly under the micromirrors is also responsible for problems of photosensitivity. As discussed in U.S. Pat. No. 6,344,672, it was found that the CMOS memory cells are unstable in a high-intensity light environment. The patent provided an active collector region in which photogenerated carriers could recombine before reaching the addressing electrode.
Reflectivity, Inc. (Sunnyvale, Calif.) is also known to be developing micromirror devices. As disclosed in U.S. Pat. No. 5,835,256, the aforementioned problems associated with placing CMOS and micromirrors on the same substrate are solved by placing the micromirrors and CMOS on different substrates. In other words, a hinge and a micromirror are fabricated on an optically transparent substrate, such that the optically reflective surface of the micromirror is proximate the optically transparent substrate. Addressing circuits including mirror addressing electrodes are fabricated on a 2nd substrate (typically silicon) and the 2 substrates are bonded together with a predetermined gap between the micromirror and the addressing electrodes.
In order to reduce scattering by non-planar surfaces and increase the fill factor, it was necessary to provide a light shield on the optically transparent substrate in the hinge areas. In an improved device according to U.S. Pat. No. 6,529,310, the hinges are placed on the side of the mirror opposite to the side that is proximate the optically transparent substrate.
However, another difficulty with the architecture of U.S. Pat. No. 5,835,256 is that the gap between the mirror and mirror addressing electrodes is difficult to control. Since the actuation force is superlinearly dependent on this gap, it is imperative to achieve uniform gap over the entire array to obtain uniform performance characteristics. As discussed in US 2003/0134449, 2nd and higher order adjustments in the gap may be needed in the manufacturing process. Such adjustments make the manufacturing process more complicated. It would be preferable to have a device architecture in which the mirror address electrodes and mirrors are disposed on the same substrate.
U.S. Pat. No. 6,523,961 also discusses the problem of mirror design for reduced diffraction. Improved mirrors are non-rectangular. Numerous non-rectangular mirrors are proposed. All of the preferred mirrors are characterized by having at least 2 sides that are parallel to the illumination axis and 2 other sides that are non-perpendicular to the illumination axis. Furthermore, it shown that the overall size and cost of the display can be reduced by placing the light source relative to the micromirror array such that the illumination axis is parallel to 2 sides of the rectangular array and perpendicular to the remaining 2 sides of the rectangular array.
U.S. Pat. No. 6,523,961 describes a potential problem with certain mirror designs, when used as pixels in a spatial light modulator. For example, if an array of square mirrors were placed at a 45 degree angle relative to the SLM's x-y grid, twice as many row or column wires to the pixel controller cells would be required compared to the case where the array were placed at a 0 degree angle relative to the x-y grid. However, this is a potential difficulty with electrical connections to the array and is not directly related to the fabrication of micromirrors.
Despite these improvements, the limitation of U.S. Pat. No. 6,523,961 is that the preferred embodiments are illustrated with respect to a device architecture in which the addressing electrodes and micromirrors are disposed on separate substrates. As discussed above, this architecture causes complications in the manufacturing process, since the gap between the mirror and the electrode must be precisely and accurately controlled within an array.
U.S. Pat. No. 5,631,782 discloses an improvement to TI's 2nd generation micromirror device. It is discussed that conventional spacervias on the mirror surface are undesirable because of diffraction effects. It would be possible to cover the spacervia by sputtering sufficiently thick films of mirror material. However, a heavier mirror requires a higher resonant reset frequency. Reset efficiency drops off significantly with increasing reset frequency, because of frequency dependent damping effects. Therefore, it is desirable to keep the mirror as light as possible. U.S. Pat. No. 5,631,782 describes a mirror support pillar in which the top of the pillar is covered and closed. Since there is no hole, this is called a pillar instead of a spacervia. The support pillar is fabricated as follows. The pillar material may be a photoresist or a dielectric such as silicon oxide, silicon nitride, or silicon oxynitride. The pillar material is deposited on the underlying substrate, and is patterned into a pillar. A metal layer is then deposited. The metal covers the pillar as well as the surrounding area. This metal layer forms the sheath of the pillar. A photoresist layer sacrificial layer is formed by spin-coating. The photoresist on the top side of the pillar can be removed by plasma etching. The etching process at the top of the pillar essentially stops when the metal layer is exposed. However, the plasma etch also etches elsewhere else on the photoresist spacer layer, and therefore a mirror layer that is subsequently deposited on top of the spacer layer is not expected to be flat. Therefore, a limitation of U.S. Pat. No. 5,631,782 is that although it provides a method to eliminate the diffraction due to spacervias, a flat mirror cannot be made since the underlying spacer layer is not flat.
It is widely known that multilayer dielectric mirrors offer superior reflectivity compared to metallic mirrors. The use of multilayer dielectric mirrors has been well documented in the fabrication of Fabry-Perot etalons and lasers for example. In the case of electromechanical micromirrors, U.S. Pat. No. 6,538,800 discloses that a 96 nm thick layer of silicon dioxide (n=1.46) on top of a 68 nm thick layer of silicon nitride (n=2.0) will enhance the reflectivity of an aluminum layer from 92% to over 95%. In addition to improving the optical performance of the micromirror, a higher reflectivity is preferred because there is less heat generated in the micromirror array from the incident light.
U.S. Pat. No. 6,538,800 also discusses the use of amorphous silicon as a sacrificial layer. It is shown that amorphous silicon can be deposited for this purpose by LPCVD in a quartz tube of a Tylan furnace. It is also shown that a xenon difluoride etch process can be used to etch amorphous silicon with a selectivity of 100 to 1. Therefore, amorphous silicon can be used successfully as a sacrificial layer in addition to photoresists, silicon oxide, silicon nitride, and silicon oxynitride.